- ESESC: ESESC is a cycle accurate architectural simulator. It models a very wide set of architectures. You can think of ESESC as sesc 2.0 with many enhancements.
- SESC: SESC is the original unmaintained cycle accurate architectural simulator. It models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation. Check the SESC website at sesc.sourceforge.net.
- RUBY-VPI: Ruby-VPI is a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through the Ruby programming language. It has been develop by Suraj Kurapati for his MS thesis. We are currently using it to build SCOORE testbenches.
Santa Cruz Out-of-Order Risc Engine. At Santa Cruz we are developing an
out-of-order SPARC V8 processor. This processor is synthesizable on FPGAs
This processor is currently being developed as part of class projects at UC-Santa Cruz, and by MASC's students.
XCACTI extends the widely used CACTI 3.2 cache power model. It uses a latch
the sense amplifier, and models different energies for read and writes. The
extensions have been used at the University of Illinois, University of
Rochester, North Carolina State University, U.C. Davis, U.C. Irvine,
U.C. Riverside, and University of Arizona.
It is available locally (xcacti.tgz), you can use for any paper or work. Let me know if you find any problem or you publish a paper using it.
- SCVTOOLS: Santa Cruz Verilog Tools. As part of the SCOORE project two verilog tools have been developed: a coverage and a lint tool.
- HDLMETRICS: HDL metrics is a GPL tool developed as a collaboration betweeen UC-Santa Cruz and University of Illinois. It reports a set of metrics for VHDL. The source code is available in hdlmetrics.tgz