Research Interests

Computer architecture, focusing on productive hardware design flows (LiveHD and ESESC), out-of-order cores, and RISC-V verification. Past projects with Thread Level Speculation, infrared thermal measurements and power modeling, and design effort metrics/models.

Looking for good MS/PhD students. We have many projects to help, contact me if you are looking for a MS/PhD thesis.

Funding MS/PhD Students

I have funding opportunities for UCSC PhD and MS students working on more productive hardware design flows. Check the current list of projects available for MS students at projects.md. Contact me if you are interested.
Besides hardware productivity, I am also looking for motivated PhD in other areas in computer architecture.

The MASC group is part of UC Santa Cruz Hardware Systems Collective. The collective is a group of researchers at the Computer Science Department investigating how to design/build/architect/secure/optimize/integrate/program the next generation of hardware.

Recent News

• Google Academic Award for Building and Evaluating Hardware Agents ($100K)
• A Productive Open Source Hardware Development Flow
• CROSS funding

Recent Selected Publications

• HDLEval Benchmarking LLMs for Multiple HDLs, Mark Zakharov, Farzaneh Rabiei Kashanaki, Jose Renau. The First IEEE International Workshop on LLM-Aided Design (ISLAD), July 2024.
• RETROSPECTIVE: Power model validation through thermal measurements, Jose Renau. ISCA@50 25-Year retrospective 1996-2020 (ISCA Retrospective), July 2023.
• A Multi-threaded Fast Hardware Compiler for HDLs, Sheng-Hong Wang, Hunter Coffman, Kenneth Mayer, Sakshi Garg, and Jose Renau. International Conference on Compiler Construction (CC), February 2023.
• Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation, Nursultan Kabylkas, Tommy Thorn (Esperanto Technologies), Shreesha Srinath (Intel), Polychronis Xekalakis (Nvidia), and Jose Renau. 54th International Symposium on Microarchitecture (MICRO), October 2021.