WELCOME TO
INTRODUCTION TO
LOGIC
DESIGN.
10 May 1999
Welcome to CE 100 (and CE 100L), Intro to Logic Design. In this class
we study the principles of digital logic circuits and we get some
design experience via labs and problem sets.
Who, what, and where:
- Instructor:
Kevin Karplus
- Office: 315b Applied Sciences
- Phone: 459-4250
- Office hours: T Th 2:00-3:00 and by appointment via email.
- Teaching Assistants:
James Christofferson and
Shuo (Shawn) Zhang .
- Texts
- Required: Digital Design: principles and practices by
John. F. Wakerly, second edition, Prentice-Hall, 1994.
- Class meetings
- lecture location: Social Sciences II Room 75
- lecture time: MWF 2-3:10
- Midterm Exam time (tentative): Wednesday, May 5 2-3:10 pm
- Final Exam time: Tuesday June 8, 8am-11am
- Newsgroup
- There is a newsgroup (
ucsc.class.cmpe100) for the class.
- For posting to the
newsgroup, it is generally better to be working from a UNIX machine
(or commercial internet provider), so that proper mailing addresses
are generated.
The assignments for the course.
Note: all assignments are due at the beginning of class on the due
date, so that we can discuss the homework problmes right after you
have struggled with them. Late homeworks will be VERY difficult for
us to deal with fairly.
- Assignment 1: due Monday, April 5.
- Read Chapter 1 and Sections 2.1-2.6, 2.8, 2.11-12, 2.14.
Do exercises 2.1, 2.5, 2.6, 2.19, 2.22, 2.25, 2.27, 2.31, 2.38.
Solutions are now available (as GIFs
scanned from the instructor's manual).
- Assignment 2: due Monday, April 12.
- Read Sections 4.1-3,4.5
Do exercises 4.7 acgi (but use Karnaugh maps, not truth tables), 4.9 ace,
4.15, 4.18, 4.27, 4.29, 4.37, 4.39, 4.41 (read 4.40 for definitions),
4.42, 4.49, 4.50, 4.59, 4.62 df, 4.64 b, 4.65 (treat the numbers as unsigned).
Solutions are now available (as GIFs
scanned from the instructor's manual).
- Assignment 3: due Monday, April 19.
- Read 3.1-3.5.2, 3.5.6-3.5.8, 3.6.2, 3.7.2, 3.7.4, 3.8
Students without any background in electricity may want to read
Electrical Circuits Review
by Bruce M. Fleischer (.pdf, 85K).
EE students and ambitious computer engineering students
may want to read all of chapter 3, since this is
the basics of digital electronics.
Do exercises 3.8, 3.11, 3.15, 3.17, 3.21, 3.39, 3.40, 3.60, 3.61,
3.62, 3.63, 3.79.
Solutions are now available.
- Assignment 4: due Monday, April 26.
- Read Chapter 5.
Do exercise 5.11, 5.15, 5.17, 5.22, 5.29, 5.35, 5.46, 5.54, 5.59,
5.61, 5.67, 5.70, 5.76
Solutions are now available.
- Assignment 5a: due Monday, May 3
- Read 6.1-6.3,6.12.
Do exercises 6.1, 6.2, 6.4, 6.20, 6.30, 6.32
Assignment 5 has been split between May 3 and
May 10, because of the midterm on May 5.
Solutions are now available.
- Assignment 5b: due Monday, May 10.
- Read 7.1, 7.2
Do exercises 7.2, 7.3, 7.4, 7.7, 7.23
solutions are now available.
- Assignment 6: due Monday, May 17.
- Read 7.3-7.4.
Do exercises 7.9, 7.11, 7.14, 7.18, 7.23, 7.25, 7.27
Solutions are now available.
- Assignment 7: due Monday, May 24.
- Read 8.1-3, 8.5
Do exercises 8.1, 8.3, 8.5, 8.6, 8.17
Solutions are now available.
- Assignment 8: due TUESDAY, June 1.
- Read 9.
Do exercises 9.2, 9.7, 9.8, 9.11, 9.12, 9.16, 9.20, 9.31, 9.45, 9.47-49
Solutions now available.
All labs meet in Applied Sciences 104. During lab you may ask for help
with your laboratory assignment or with your written homework.
The laboratory assignments for the course.
Special deal: If you turn in your lab report on time, you get an extra
5% for each day ahead of schedule that you demonstrate your lab to
your TA (up to 25% extra credit)!
The TAs have put together a
web site with useful information about the labs.
This site is still undergoing revision, as we thrash out some details
about the labs.
-
Lab 1. Simple logic gates. Now available.
-
Lab 2. Full adder. Now available.
-
Lab 3. 4-bit adder/subtractor. Now available.
-
Lab 4. 4-bit ALU with register. Now available.
There is also an important
tutorial,
that you should read before doing the lab.
-
Lab 5 Oscilloscope usage. Now available, except for prelab 6.
-
Lab 6. Sawtooth generator with digital-to-analog converter.
(Note: see lab 7 for prelab for next week.)
-
Lab 7. Finite-state machine design.
(Note: see lab 8 for prelab for next week.)
-
Lab 8. Successive-approximation analog-to-digital conversion.
Lab reports should be turned in as
postscript files. To do this, you
can use any program available to you, but you might like to try a
latex file . In any case, here is the
postscript or
pdf for a fictitious lab report (generated from the latex
source previously cited). I checked and LaTeX is
available on the cats machines. No matter what you use, you
should check your method by making sure you can successfully read
postscript that you mail yourself using the ghostview program
available on the CATS machines (such as those in AS215).
Steve Petersen has written a useful
note
on how to survive lab classes.
What we are going to look at.
Below is the expected syllabus for this course to give you an idea of
which topics will be discussed when.
We may deviate a bit from this depending on class feedback.
- Week 1: Counting and codes(2.1-2.6,2.8,2.11-12,2.14)
- Week 2: Boolean algebra, minimization, and Karnaugh maps (4.1-4.3,4.5)
- Week 3: Basic electronics and logic gates (some of 3)
You may want to read
Electrical Circuits Review
by Bruce M. Fleischer (.pdf, 85K).
- Week 4: Combinational logic design practices (5)
- Week 5: Programmable logic devices (PLA, PAL, ..) (6.1-6.3, 6.12)
- Week 6: MIDTERM Sequential elements (latches and flip-flops) (7.1 -7.2)
- Week 7: Sequential logic design (7.3 - 7.4)
- Week 8: Sequential logic design practices (8.1 - 8.3, 8.5)
- Week 9: More sequential design (9)
- Week 10:Asynchronous sequential design (7.5 - 7.6)
CE home
CMPE 100 home page
Questions about page content should be directed to
Kevin Karplus
Computer Engineering
University of California, Santa Cruz
Santa Cruz, CA 95064
USA
karplus@cse.ucsc.edu
1-831-459-4250