CMPE 100 Lab #4
Report due by midnight April 30

There is also an important tutorial, that you should read before doing the lab.

Description

In this lab you will add a register to store the results of the adder/subtractor you built in the previous lab. You will also add 3 functions to the circuit: A AND B, A OR B, and A XOR B. Your ALU (Arithmetic Logic Unit) will have three control inputs to select which of the 5 functions is active. Instead of building a prototype out of discrete logic, you will download your design to the Xilinx FPGA.

The encodings of the select inputs S[2:0] are as follows:
S function
000 A+B
001 A-B
010 A AND B
100 A OR B
111 A XOR B

The inputs to the circuit will be A[3:0], B[3:0], S[2:0], and CLOCK for updating the register. Your outputs will be R[3:0], your 4-bit result, a 1-bit carry-out, and a 1-bit overflow signal.

The carry-out bit should be a direct output from the top bit of your adder. It is easy to interpret if the inputs A and B are treated as unsigned numbers. When adding two unsigned numbers, the carry-out bit is set if the correct sum is not representable in 4 bits. When subtracting two unsigned numbers, the carry-out bit is set if the result is >=0.

The overflow bit only makes sense when interpreting the inputs as twos-complement numbers. The overflow bit should be high when the correct output of adding or subtracting the two twos-complement arguments is not representable as a 4-bit twos-complement number. It should always be zero for the logical operations (AND, OR, XOR).

Lab4 prelab

  1. Work out the correct definition for the overflow bit and provide a logic formula for it.
  2. You and your partner should generate a complete 'top level' block diagram of the enhanced ALU and register. This diagram should explicitly show the major functional hierarchy blocks, their interconnections, as well as the multiplexer and the output buffer (the register). It is probably best to do the hierarchy as a bit-slice design, so that you can just array n "alu_slice" cells to get an n-bit alu.

Lab Work

Software and Simulation:

  1. You will be inputing and simulating, one block at a time. Start with the 4-bit adder subtractor that you have built in the previous lab. Test this block for all possible faults. You can test an adder without generating all possible 2n input combinations, by using the test vectors in the following table1:

    Vector CarryIn0 A0B0 A1B1 A2B2 A3B3
    t0 000000000
    t1 001010101
    t2 010101010
    t3 011001100
    t4 100110011
    t5 101010101
    t6 110101010
    t7 111111111

    Can you see why this covers all possible faults? Save the results of the simulation and include it in your lab report.

  2. Create the hierarchy cells for the functional blocks of the AND, OR, and XOR functions. Test them in a way that is similar to the adder test (you only need 4 test vectors). Save the results of the simulation for each functional block and include in your lab report.
  3. Now put the pieces together. Create a new sheet, add the hierarchy blocks from your parts library, and finally add the register and the multiplexer.
  4. Verify the final design by executing all functions on a few input values, save the simulation results to show to the TA during the demonstration. Be sure that your test set demonstrates the correct operation of the overflow and carry bits. Note: the TA may ask you to try out certain test vectors that you did NOT originally include.

Hardware:

  1. Read the tutorial and understand how to download a design into the FPGA
  2. Download your design and show the working circuit to the T.A. Use the hex displays for your result, and LEDs for the carry-out and overflow signals.

Lab5 prelab

  1. Read and understand the use of the oscilloscope from the following links:

    Note: We are not using a Tektronix scope in the lab, but almost all scopes have the same buttons and knobs.

  2. Submit answers to the following questions:
    1. Suppose I want to view a waveform of 5V peak to peak at 1 MHz. What would be a good setting for the Time/Div and V/div to view the waveform?
    2. What is the difference between CHOP and ALT?
    3. What is the x10 switch on the scope probe used for?
    4. What is the difference between AC and DC coupling?

Report

The report should include a block diagram of the circuit and a logic diagram of a single, complete bit of the ALU and register making it clear how the bits are connected. Describe how your circuit worked and any problems encountered in the lab. Include the simulation results for all of the functional blocks. Explain the methodology behind your design and prototyping process.

Submit your lab report as a postscript (or HTML) file by e-mailing it as an attachment to the TA of your lab section. Also, submit the prelab for next week's lab assignment.

1 These vectors are a standard method of testing. For more information, read some of the following articles:
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Questions about page content should be directed to

Kevin Karplus
Computer Engineering
University of California, Santa Cruz
Santa Cruz, CA 95064
USA
karplus@cse.ucsc.edu
1-831-459-4250