CE121 -- Microprocessor System Design
Assignment 4
Out: January 29, 1997
Due: February 5, 1997

1. (30 points) 4.19 and 4.20, but instead populate a 192-megabyte memory system with 16-megabit DRAM chips.
   1. 4.19.
   2. 4.20. Consider 8-, 32-, and 64-bit words.
   3. What is the MTBF for the systems in 4.20? Consider both the mean time between detectable or correctable errors, and the mean time between true failures (what constitutes true failure of an ECC?).
2. (45 points) Page mode in the MCM516100-70 DRAM is considerably faster than normal random access. Suppose that the DRAM has been enhanced with support circuitry for and timing (with the circuitry similar to that of the last assignment). In addition to address, / , and signals, this logic also has an input which, when asserted, indicates that page mode should be used, in which case the upper address bits are ignored. Assume that this enhanced DRAM chip does not change the timing at all from the datasheet (ha!), except that for the circuit to work, it always holds asserted until the start of the next request to see whether or not page mode is desired.

   Consider a microprocessor with a 32-bit memory bus, a 128Mbyte memory bank that is 4 bytes wide, and a simplified semi-synchronous bus cycle in which, in a no-wait bus cycle, there is a 0.5 clock period overhead, 2 clock periods for data access time, and a final 0.5 clock period overhead. Assume that the microprocessor requests one memory operation (read or write) per bus cycle. (See the figure.)

   

   The interface logic drives the DRAM at its fastest possible speed, and all its delays are accounted for in the 1-clock overhead to the bus cycles.

   1. Design circuitry to decide whether or not page mode can be used for each memory request. Design it so that it can be assumed to correctly assert in 0.5 clock cycles. Use a databook to find maximum delay times for your selected parts.
   2. For a clock speed of 10MHz, how many wait states are needed without your circuit? How many for sequential and random addresses with your circuit? Thoroughly justify your answer, being sure that all timing constraints are met (the most important are likely to be access time and cycle time). An annotated timing diagram would help.
   3. For 25MHz?
   4. For 50MHz?
   5. Assuming the 50MHz clock, suppose that all memory accesses come in groups 4 sequential accesses (the microprocessor has a 4-word cache line). What is the memory bandwidth (Mbytes per second) with and without your circuit? What speedup did you gain?
3. (15 points) Draw a logic level versus time diagram for a 9600 baud RS232 transmission of the ascii characters "CE!". What is the total time taken to transmit these characters assuming 8 data bits, odd parity, 1 start and 0.5 stop bits?