CE121 -- Microprocessor System Design
Assignment 3
Out: January 22, 1997
Due: January 29, 1997

1. (15 points) Problem 3.4 for the 3MHz HC11. Calculate the number of wait states (if they were available) that would be required, as well as how much you would have to slow the clock to enable a 0-wait access.
2. (15 points) Problem 4.4 of the text.
3. (30 points) Problems 4.6 and 4.7 in the text. Assume that the microprocessor is an HC11 (how fast can it be clocked?).
   1. Draw the circuits and a timing diagram, including the HC11. The circuits may be at a very high level (i.e., no pin identifications, bundled database and address bus, and so forth).
   2. Answer 4.6.
   3. Answer 4.7.
4. (30 points) Problem 4.11. The circuit should include a refresh counter to go through all refresh addresses, and take as inputs a read/write signal, a device select, an appropriate number of address lines, and a refresh signal. Whenever refresh is asserted, the address and read/write signals are ignored, and instead the next line of the DRAM (according to the counter) is refreshed.