CE121--Microprocessor System Design
Assignment 2
Out: January 15, 1997
Due: January 22, 1997

1. (20 points) Calculate the following based on the 8MHz 68008 timing data in the text.
   1. Maximum time between assertion and assertion for the 0-wait write bus cycle.
   2. Minimum time in a 0-wait write bus cycle between assertion and data deassertion. Calculate the value for the 28, 14A, 22,25 path and explain why this is an incorrect calculation.
   3. Calculate and justify at least two other ways to arrive at the assertion to data deassertion time. Explain what value to use in a design and why.
2. (10 points) For the HC11 at 1MHz, what is the minimum time available between address strobe assertion and data required during a write? Explain.
3. (30 points) Using SSI/MSI components, show how to connect an 8-bit I/O device to an HC11 bus. Use transceivers (e.g., '245) and buffers (e.g., '244) between the device and the bus. The device has control inputs and : on the falling edge of these signals the device will read or write data. The device has asynchronous control outputs and , which indicate when the device is ready to write or read information. When the device is not ready, it will ignore the and signal. Strictly obey signal definitions, as other devices will be using the bus. The device is to be located at FFF77D. Include a neat timing diagram to illustrate the features of your design.
4. (30 points) This question considers address and data bus loading of the HC11. Assume that only the parts mentioned in the problem are connected to the data and address bus (e.g., no decoders are used). The relevant data can be found in the datasheets on the class WWW page. For the HC11, the electrical data (appendix A) begings on page 121.
   1. With 8 Hitachi 6862-12 SRAMs attached to the bus, and considering only current, how many 74LS373 latches can be attached directly to the HC11?
   2. What is the load capacitance on the address and on the data bus, assuming an additional 3pF per chip for trace capacitance?
   3. Based on the bus capacitance test loads specified in the HC11 data sheet and the results of part (b), how many latches can be attached directly to the HC11?