Computer architecture, focusing on productive hardware design flows (LiveHD and ESESC), out-of-order cores, and
RISC-V verification. Past projects with Thread Level Speculation, infrared thermal measurements and power
modeling, and design effort metrics/models.
Looking for good MS/PhD students. We have many projects to help, contact me if you are looking for a MS/PhD thesis.
Funding MS/PhD Students
I have funding opportunities for UCSC PhD and MS students working on
more productive hardware design flows. Check the current list of
projects available for MS students at projects.md. Contact me if you are interested.
Besides hardware productivity, I am also looking for motivated PhD in other areas in computer architecture.
The MASC group is part of UC Santa Cruz Hardware Systems Collective. The
collective is a group of researchers at the Computer Science Department investigating how to
design/build/architect/secure/optimize/integrate/program the next generation of hardware.
A Productive Open Source Hardware Development Flow
NSF SHF Cascode Supporting and Leveraging Voltage Stacking in Future Microprocessors ($285K)
Recent Selected Publications
A Multi-threaded Fast Hardware Compiler for HDLs,
Sheng-Hong Wang, Hunter Coffman, Kenneth Mayer, Sakshi Garg, and Jose Renau. International Conference on Compiler Construction (CC), February 2023.
Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation,
Nursultan Kabylkas, Tommy Thorn (Esperanto Technologies), Shreesha Srinath (Intel), Polychronis Xekalakis (Nvidia), and Jose Renau. 54th International Symposium on Microarchitecture (MICRO), October 2021.
LiveHD: A Productive Live Hardware Development Flow,
Sheng-Hong Wang, Rafael T. Possignolo, Haven Blake Skinner, and Jose Renau, IEEE Micro magazine (MICRO Magazine), June 2020.
LiveSim: A Fast Hot Reload Simulator,
Haven Skinner, Rafael T. Possignolo, Sheng-Hong Wang, and Jose Renau, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2020.