Computer architecture, including design effort metrics and models, infrared thermal measurements and modeling, simulation, FPGA/ASIC design, and mobile pervasive computing.
Looking for good MS students. We have many projects to help, contact me if you are looking for a MS thesis.
Future Conference Deadlines
A list of computer architecture conferences.
WikiCFP for computer architecture.
WikiCFP for design automation.
A map of computer architecture conferences.
NSF SHF Cascode Supporting and Leveraging Voltage Stacking in Future Microprocessors ($285K)
Recent Selected Publications
SMatch: Structural Matching for Fast Resynthesis in FPGAs,
Rafael T. Possignolo, and Jose Renau, Design Automation Conference (DAC), June 2019.
Live Graph infrastructure for Synthesis and Simulation,
Jose Renau, Latch-Up conference (Latch-Up), May 2019.
GPU NTC Process Variation Compensation with Voltage Stacking,
Rafael T. Possignolo, Elnaz Ebrahimi, Ehsan Ardestani, Alamelu Sankaranarayanan, Jose Luis Briz, Jose Renau. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018.
Architectural Opportunities for Novel Dynamic EMI Shifting (DEMIS),
Daphne I. Gorman, Jose Renau, and Matthew Guthaus. 50th International Symposium on Microarchitecture (MICRO), October 2017.