Computer architecture, focusing on productive hardware design flows (LiveHD and ESESC), out-of-order cores, and
RISC-V verification. Past projects with Thread Level Speculation, infrared thermal measurements and power
modeling, and design effort metrics/models.
Looking for good MS/PhD students. We have many projects to help, contact me if you are looking for a MS/PhD thesis.
Funding MS/PhD Students
I have funding opportunities for UCSC PhD and MS students working on
more productive hardware design flows. Check the current list of
projects available for MS students at projects.md. Contact me if you are interested.
Besides hardware productivity, I am also looking for motivated PhD in other areas in computer architecture.
The MASC group is part of UC Santa Cruz Hardware Systems Collective. The
collective is a group of researchers at the Computer Science Department investigating how to
design/build/architect/secure/optimize/integrate/program the next generation of hardware.
A Productive Open Source Hardware Development Flow
NSF SHF Cascode Supporting and Leveraging Voltage Stacking in Future Microprocessors ($285K)
Recent Selected Publications
EMI Architectural Model and Core Hopping,
Daphne I. Gorman, Rafael T. Possignolo, and Jose Renau. 52th International Symposium on Microarchitecture (MICRO), October 2019.
SMatch: Structural Matching for Fast Resynthesis in FPGAs,
Rafael T. Possignolo, and Jose Renau, Design Automation Conference (DAC), June 2019.
Live Graph infrastructure for Synthesis and Simulation,
Jose Renau, Latch-Up conference (Latch-Up), May 2019.
GPU NTC Process Variation Compensation with Voltage Stacking,
Rafael T. Possignolo, Elnaz Ebrahimi, Ehsan Ardestani, Alamelu Sankaranarayanan, Jose Luis Briz, Jose Renau. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018.