Pak K. Chan, Martine D. F. Schlag, Carl Ebeling and Larry McMurchie.
Distributed-Memory Parallel Routing for Field-Programmable Gate Arrays.
IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems.
Vol. 19, No. 8, pgs. 850-862, August 2000.
2.
Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan.
Multi-level Spectral Hypergraph Partitioning with Arbitrary Vertex Sizes.
IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems.
Vol. 18, No. 9, pgs. 1389-1399, September 1999.
3.
Pak K. Chan, Martine Schlag, Jason Y. Zien.
Spectral-Based Multiway FPGA Partitioning.
IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems.
Vol. 15, No. 5, pgs. 554-559, May 1996.
4.
Martine Schlag and F. Joel Ferguson.
Detection of Multiple Faults in Two-Dimensional ILAs.
IEEE Transactions on Computers. Vol. 45, No. 6, June 1996 pgs. 741-745.
5.
Pak K. Chan, Martine Schlag and Jason Y. Zien.
Spectral K-Way Ratio-Cut Partitioning and Clustering.
IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems. Vol. 13, No. 9, September 1994 pgs. 1088-1096.
6.
Martine Schlag, Pak K. Chan and Jackson Kong.
Routability-Driven Technology Mapping for LookUp Table-Based FPGAs.
IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems. Vol. 13, No. 1, January 1994 pgs. 13-26.
7.
Martine Schlag, Pak K. Chan and Jackson Kong.
Empirical Evaluation of Multi-level Logic Minimization Tools for a
Lookup Table-based Field-Programmable Gate Array Technology.
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems. Vol. 12, No. 5, May 1993 pgs. 713-721.
8.
Richard Anderson, Simon Kahan and Martine Schlag. Single-Layer
Cylindrical Compaction. Algorithmica. Vol. 9, 1993 pgs. 293-312.
9.
Pak K. Chan, Martine D.F. Schlag, Clark D. Thomborson and Vojin G.
Oklobdzija. Delay Optimization of Carry-Skip Adders and Block
Carry-Lookahead Adders using Multi-dimensional Dynamic Programming.
IEEE Transactions on Computers special issue on Computer
Arithmetic. Vol. 41, No. 8, August 1992 pgs. 920-930.
10.
Pak K. Chan and Martine D.F. Schlag.
A Note on Designing Two-Level Carry-Skip Adders.
Journal of VLSI Signal Processing. No. 3, 1991, pgs. 275-281.
11.
Pak K. Chan and Martine D.F. Schlag. Analysis and Design of CMOS
Manchester Adders with Variable Carry-Skip. IEEE Transactions on
Computers special issue on Computer Arithmetic. Vol. 39, No. 8,
August 1990, pgs. 983-992.
12.
Pak K. Chan and Martine Schlag. Bounds on Signal Delay in RC
Mesh Networks. IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems. Vol. 8, No. 6, June 1989 pgs. 581-589.
13.
Y. F. Wu, P. Widmayer, M. D. F. Schlag, and C. K. Wong. Rectilinear
Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear
Obstacles. IEEE Transactions on Computers Vol. C-36 No. 3 pgs. 321-332.
March 1987.
14.
P. Widmayer, Y. F. Wu, M. D. F. Schlag and C. K. Wong. On some union
and intersection problems for polygons with fixed orientation.
Computing 36, 1986 pgs. 183-197.
15.
M. D. F. Schlag, E. J. Yoffa, P. S. Hauge, and C. K. Wong. A Method
for Improving Cascode-Switch Macro Wirability. IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems Vol. CAD-4 No.2
pgs. 150-155. April 1985.
16.
M. Schlag, F. Luccio, P. Maestrini, D. T. Lee and C. K. Wong.
A Visibility Problem in VLSI Layout Compaction. Advances in Computing
Research, Vol. II, VLSI Theory, ed. Franco P. Preparata, JAI Press
Inc. 1984.
17.
M. D. F. Schlag, L. S. Woo and C. K. Wong. Maximizing Pin Alignment
by Pin Permutations. Integration, the VLSI Journal Vol. 2 1984
pgs. 279-307.
18.
M. Schlag, Y. Z. Liao and C. K. Wong. An Algorithm for Optimal
Two-Dimensional Compaction of VLSI Layouts. Integration, the VLSI
Journal Vol. 1 No. 2&3 (Oct. 1983) 179-209.
Pak K. Chan and Martine D.F. Schlag.
New Parallelization and Convergence Results for NC: A Negotiation-Based
FPGA Router.
FPGA'2000: International Symposium on Field-Programmable Gate Arrays.
Monterey, California, February 2000.
2.
Jason Zien, Pak K. Chan, and Martine Schlag.
Hybrid Spectral/Iterative Partitioning.
Proceedings of IEEE/ACM International Conference on
Computer-Aided Design. San Jose, California, November 1997. pgs. 436-440.
3.
Pak K. Chan and Martine Schlag.
Acceleration of an FPGA router.
IEEE Symposium on FPGAs for Custom Computing Machines.
Napa, California, April 1997.
4.
Jason Zien, Martine Schlag, and Pak K. Chan.
Multi-level Spectral Hypergraph Partitioning with Arbitrary Vertex Sizes.
Proceedings of the IEEE/ACM International Conference on
Computer-Aided Design. San Jose, California, November 1996, pgs. 201-204.
5.
Pak K. Chan and Martine Schlag.
Spectral-based multi-way FPGA partitioning.
FPGA'95: International Symposium on
Field-Programmable Gate Arrays. Monterey, California, February 1995.
6.
Aaron Ferrucci, Marcelo Martin, Tom Geocaris, Martine Schlag
and Pak K. Chan. A Field-Programmable Gate Array Implementation os
a Self-Adapting and Scalable Connectionist Network.
FPGA'94: International ACM/SIGDA Workshop on
Field-Programmable Gate Arrays. Berkeley, California, February 1994.
7.
Pak K. Chan, Martine D.F. Schlag, and Jason Zien.
Spectral K-way Ratio-Cut Partitioning and Clustering.
30th Design Automation Conference, Dallas Texas, June 1993.
8.
Pak K. Chan, Martine D.F. Schlag, and Jason Zien.
On Routability Prediction for Field-programmable Gate Arrays.
30th Design Automation Conference, Dallas Texas, June 1993.
9.
Pak K. Chan and Martine Schlag.
Architectural tradeoffs in field-programmable-device-based computing systems.
IEEE Workshop on FPGAs for Custom Computing Machines,
Napa, California, April 1993.
10.
Pak K. Chan, Martine D.F. Schlag, and Jason Zien.
Spectral K-way Ratio-Cut Partitioning.
Advanced Research in VLSI: Proceedings of the Symposium on Integrated
Systems. eds. Carl Ebeling and Gaetano Borriello.
The MIT Press, Cambridge MA. March 1993, pgs. 123-142.
11.
Martine Schlag, Jackson Kong and Pak K. Chan.
Routability-Driven Technology Mapping for LookUp Table-Based FPGAs.
1992 IEEE International Conference on Computer Design:
VLSI in Computers and processors.
Cambridge, Massachusetts, October 1992, pgs. 86-90.
12.
Pak K. Chan, Martine Schlag, and Marcelo Martin. BORG: A
Reconfigurable Prototyping Board using Field-Programmable Gate Arrays.
FPGA'92: First International ACM/SIGDA Workshop on
Field-Programmable Gate Arrays,
Berkeley, California, February 1992, pgs. 47-51.
13.
Martine Schlag, Pak Chan, Jackson Kong. Empirical Evaluation of
Multilevel Logic Minimization Tools for a Field-Programmable Gate
Array Technology.
FPGAs: Oxford 1991 International Workshop on Field-Programmable Logic
and Applications. ed. Will R. Moore, Abingdon CS&EE Books,
Abingdon England, 1991 pgs. 201-213.
14.
Pak K. Chan, Martine D.F. Schlag, Clark D. Thomborson and Vojin G.
Oklobdzija. Delay Optimization of Carry-Skip Adders and Block
Carry-Lookahead Adders. 10th Symposium on Computer Arithmetic,
Grenoble, France, June 1991 pgs. 154-164.
15.
Martine Schlag and F. Joel Ferguson. Detection of all multiple
faults in two-dimensional logic arrays. Advanced Research in VLSI:
Proceedings of the 1991 University of California, Santa Cruz Conference.
ed. Carlo Sequin. pgs. 19-34, The MIT Press, Cambridge MA. March 1991.
16.
Richard Anderson, Simon Kahan and Martine Schlag. An O(n log n)
algorithm for 1-D tile compaction. In Proceedings of the
International Conference on Computer-Aided Design, Santa Clara,
California, November 1989, pgs. 144-147.
17.
Pak K. Chan and Martine D.F. Schlag. Analysis and Design of CMOS
Manchester Adders with Variable Carry-Skip. Proceedings of the 9th
Symposium on Computer Arithmetic, Santa Monica, California, September 1989
pgs. 86-95.
18.
Pak K. Chan, Wayne Dai, Joel Ferguson, Daniel Helman, Kevin
Karplus and Martine Schlag. VLSI and CAD Education at UC Santa Cruz.
In Proceedings of the 1989 VLSI Education Conference and Exposition,
Santa Clara, California. July 1989 pgs. 139-148.
19.
Martine Schlag. The planar topology of functional programs.
The Third Functional Programming Languages and
Computer Architecture Conference Portland, Oregon, September 1987.
Lecture Notes in Computer Science, ed. Gilles Kahn pgs. 174-193, Springer-Verlag Berlin 1987.
20.
D. Patel, M. Schlag, and M. Ercegovac. nuFP: An Environment for the
Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms.
Functional Programming Languages and Computer Architecture Conference,
Nancy, France, September 1985. Lecture Notes in Computer
Science, ed. J. Jouannaud pgs. 238-255, Springer-Verlag Berlin 1985.
21.
M.D. Ercegovac, P.K. Chan, Z. Konstantinovic, T.M. Ravi
and M.D.F. Schlag, Task Partitioning, Allocation and Simulation for a
Dataflow Multimicroprocessor System. In Summer Computer Simulation
Conference, Boston 1984.
22.
M. Schlag, Y. Z. Liao and C. K. Wong. An Algorithm for Optimal
Two-Dimensional Compaction of VLSI Layouts. In Proceedings of
the International Conference on Computer-Aided Design, Santa Clara,
California September 1983, pgs. 88-89.