I am highly passionate and self driven student, I strongly believe in learning practically with diligence and intend to make a difference through my research work.
Trained by: Dr. Amit Bhatt (Professor)
Designed a 5 Stage Pipelined Processor, capable of performing Arithematic, Logical, Memory and Branch instructions. Designed in Xilinx ISE Design Suite and synthesis using Cadence Synthesis Tool.
Trained by: Dr. Padmanaban K
Trained in: Verilog and SystemVerilog, The Training covered RTL design and Functional Verification using SystemVerilog. It provided hands on experience with building Testbenches; Verification Environment; CRCD and Assertion based Verification using various Design and verification projects. It also introduced the basic concepts of UVM and Scripting.
Worked on developing efficient hearing aid based on Bone conduction technology