The assignments for the course.

All reading assignments have now been updated to refer to the THIRD edition of Wakerly's book. There has been some significant reorganization of the material in the book, so be sure you have the right edition.

Assignment 0: due Friday, March 31.

Read Chapter 1 and Sections 2.1-2.6, 2.8, 2.11-12, 2.14.

Assignment 1: due Friday, April 7.

Read Sections 4.1-3,4.5
Do exercises 2.3, 2.5, 2.7, 2.20, 2.24, 2.26, 2.28, 2.32, 2.33, 2.39.
Solutions have been posted to the solutions directory. (Look for hw1-pg1.gif through hw1-pg7.gif.)

Assignment 2: due Friday, April 14.

Read 5.1-5.6, skipping subsections dealing with ABEL and VHDL.
Do exercises 4.8 (but use Karnaugh maps, not truth tables), 4.10 bdf, 4.19, 4.33, 4.34, 4.43, 4.46, 4.66 (treat the numbers as unsigned), 4.72bce, 4.83

Assignment 3: due Friday, April 21.

Read 5.7-5.11, skipping subsections dealing with ABEL and VHDL, 6.1.
Do exercises 5.10, 5.13, 5.18, 5.19, 5.22, 5.31, 5.34, 5.36 and 5.37, 5.45, 5.68

Assignment 4: due Friday, April 28.

Read 3.1-3.5.2, 3.5.6-3.5.8, 3.6.2, 3.7, 3.8 Students without any background in electricity may want to read Electrical Circuits Review by Bruce M. Fleischer (.pdf, 85K). EE students and ambitious computer engineering students may want to read all of chapter 3, since this is the basics of digital electronics.
Do exercises 5.46, 5.71, 5.74, 5.79 (hint: replace 32 by n and get a recursive equation that use can solve with the techniques from CMPE 16), 5.82 (note: the circuit must have 4 outputs, one for each of the functions), 5.83, 5.84, 5.91, 6.1 (there are 2 solutions with different data loading---show both), 6.2 (hint: 4-to-1 mux).

Assignment 5: due Friday, May 5

Read 7.1-7.5.
Do exercises 3.13, 3.16 and 3.17, 3.20, 3.32, 3.39 and 3.40, 3.59, 3.62, 3.63, 3.80, 5.55 and 5.56

Assignment 6: due Friday, May 12.

Read 7.6-7.8, 8.
Do exercises 7.2 and 7.3, 7.4, 7.7, 7.9 and 7.29, 7.13, 7.14, 7.16, 7.27, 7.30 (I think 8 states are enough---10 seems like overkill), 7.34

Assignment 7: due Friday, May 19.

Read Chapters 8 and 9.
7.20, 7.56, 7.64, 8.5 and 8.6, 8.13

Assignment 8: due Friday, May 26.
Read Sections 10.1-10.4, 10.6 (We won't cover all of the RAM timing, but you'll see it again in 121)
Do exercises 8.10, 8.20, 8.24 (don't just describe the inherent problem, but come up with a feasible solution), 8.32-34, 8.36, 8.41-42, 8.66, 8.68 (the "order of bit transmission" is a bit misleading---the design requested is an iterative one, not a sequential one---what the question does information flow from high-order bits to low-order bits or from low to high?), 8.80, 8.91-93

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