Graduate student of computer engineering at the University of California, Santa Cruz
Performance Modelling of SOC
Worked as Design Engineer at Xilinx (Jul'16 - Aug'18)
Designed and Implemented Real Time Clock Block
Pipelined Processor Design
Simulated and Designed The Layout Of 2 Stage Amplifier
High Speed Comparator Circuit Design
When I am not working, I like playing sports,dancing and writing.
I have played basketball and cricket in the school and undergrad college.
I have no publications as of now so posting seminal papers
GPU NTC Process Variation Compensation with Voltage Stacking
Architectural Opportunities for Novel Dynamic EMI Shifting