We have developed a structural design language for use in undergraduate computer architecture classes that has much of the power of VHDL with little of the complexity. This language, esim, allows students to build arbitrarily complex digital logic designs using simple hierarchical design techniques. Students can simulate and debug their designs using a simulator implemented as a Tcl module. Because esim was not intended for designing and building physical circuits, it omits many of the primitives necessary for "real" hardware design and instead focuses on the concepts necessary for teaching students about digital designs.
We have used esim as a teaching tool in undergraduate computer architecture classes at the University of Maryland Baltimore County for several semesters. Students in these classes have implemented projects as complex as a pipelined RISC processor and a full 16x16 combinational multiplier. The compiler and simulator for the language are freely distributable, and may be expanded using standard Tcl packages and Tcl code. Current simulator modules include one for displaying signal values on the screen; modules that graph signal values are planned.
A paper on esim appeared at the 2000 Workshop on Computer Architecture Education in Vancouver, Canada in June 2000.
The esim package can be installed on Linux and (possibly) on other varieties of Unix such as *BSD and Solaris. Instructions for downloading and installing the package are available online.
There is documentation on how to create digital design projects in esim. This page explains esim's syntax and gives some simple examples of esim "programs".
The esim package requires that users first compile, then simulate their designs. The esim simulator, which is implemented as a set of Tcl extensions, is documented here.
The esim language is currently reasonably stable, and we don't know of any bugs in the simulator (but please let us know if you find one). However, the interface to the simulator could certainly use some work. One of the biggest projects is to use the Tk package BLT to graph the values of signals over time. This would be very useful for students trying to debug their designs. We will take advantage of the BLT features for X-Y graphs and vectors to draw zoomable, scrollable signal traces.
Another long-term goal is the construction of a Tk frontend to a CPU simulated with esim. This frontend will make it easier for students to debug their CPUs, and could be designed to look like a frontend to a software-level simulator. By stepping through hardware & software simultaneously, students may be able to catch bugs faster.
Feedback and suggestions for further development of the esim language are welcome. Please send your comments to email@example.com.