Aditi Sinha

UCSC email:

I am a first year Computer Engineering M.S student at the University of California, Santa Cruz. My interests are in the areas of logic design and computer architecture. Currently I am enrolled in two courses; CMPE202 (Computer Architecture) and CMPS201 (Analysis of Algorithms). Planning to take CMPE220 (Advanced Parallel Processing) and CMPE221 (Advanced Microprocessor Design) in the near future. Actively seeking summer internships in 2019.


University of California, Santa Cruz

M.S., Computer Engineering

Shri Govindram Seksaria Institute of Technology and Science - Indore, India

B.E., Electronics and Telecommunications Engineering



C, C++, Embedded C, Verilog HDL, VHDL


Xilinx ISE, MATLAB, Keil ┬ÁVision


Tessolve Semiconductor Pvt. Ltd.

  • Gained insight into design methodologies, behavioral modeling and writing synthesizable RTL code
  • Studied finite state machines for applying sequential logic.
  • Implemented the APB protocol using Verilog HDL.
Seminal Papers

ESESC: A Fast Multicore Simulator Using Time-Based Sampling

  • This work presents Time-Based Sampling (TBS), a framework that is the first to enable sampling in simulation of multicore processors with virtually no limitation in terms of application type (multiprogrammed or multithreaded), number of cores, homogeneityor heterogeneity of the simulated configuration (4.99% error averaged across all the evaluated configurations).

A new organization for a perceptron-based branch predictor and its FPGA implementation

  • This work talks about dynamic branch predictors and how improvement in their prediction accuracy can be achieved through unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level.
I enjoy cooking, traveling and reading science fiction.