KARTIK JAIN

I am highly passionate and self driven student, I strongly believe in learning practically with diligence and intend to make a difference through my research work.


Experience

Reasearch Intern

Dhirubhai Ambani Institute of Information and Communication Technology

Trained by: Dr. Amit Bhatt (Professor)

Designed a 5 Stage Pipelined Processor, capable of performing Arithematic, Logical, Memory and Branch instructions. Designed in Xilinx ISE Design Suite and synthesis using Cadence Synthesis Tool.

May 2018 - July 2018

SystemVerilog Verification Trainee

Mentor Graphics

Trained by: Dr. Padmanaban K

Trained in: Verilog and SystemVerilog, The Training covered RTL design and Functional Verification using SystemVerilog. It provided hands on experience with building Testbenches; Verification Environment; CRCD and Assertion based Verification using various Design and verification projects. It also introduced the basic concepts of UVM and Scripting.

June 2017 - July 2017

Intern

WE HEAR

Worked on developing efficient hearing aid based on Bone conduction technology

December 2016 - March 2017

Technical Team Member

Robocon LDCE

September 2015 - June 2017

Education

University of California, Santa Cruz

Masters of Science
Computer Engineering

GPA: -

Sept 2018 - Present

L.D. College of Engneering

Bachelors of Engineering

GPA: 7.97/10

August 2014 - May 2018

Skills

Programming Languages
C, C++, Verilog, System Verilog.
Script
Shell,Perl.
Tools
ISE Design suit, Questasim, Modelsim, Vivado, Altera max+, MATLAB, Atmel Studios.

Interests

Playing Tennis

Travelling