UCSC School of Engineering
1156 High Street, MS:SOE3
Santa Cruz, CA 95064
Office: E2 319
Phone: 831-459-2217
Fax: 831-459-4829
Email: cyrus@soe.ucsc.edu
Courses:
|
Class Number |
Title |
# of Times Taught |
| CMPE 3 | Personal Computer Concepts: Software and Hardware | 2 |
| CMPE 12/12L | Introduction to Computer Systems and Assembly Language | 11 |
| CMPE 100/100L | Logic Design | 3 |
| CMPE 123 | Advance Microprocessor System Design | 6 |
| CMPE 123A | Engineering Design I | 5 |
| CMPE 123B | Engineering Design II | 5 |
| CMPE 222 | VLSI Digital System Design | 1 |
Research Interests:
Microprocessor architectures, ASIC design, FPGA and Microcontroller
based embedded systems
Publications:
2006 “Printed
Circuit Board Layout Time Estimation”, Cyrus Bazeghi and Jose Renau, 7th
Workshop on Complexity-Effective Design (WCED), held in conjunction with
ISCA-33, June 2006.
"SCOORE: Santa Cruz Out-of-Order RISC Engine,
FPGA Design Issues", Francisco J.
Mesa-Martinez, Abhishek Sharma, Andrew W. Hill, Carlos A. Cabrera, Cyrus
Bazeghi, Hari Kolakaleti, Joseph Nayfach, Keertika Singh, Kevin S. Halle,
Matthew D. Fischler, Melisa Nuñez, Sangeetha Nair, Suraj Narender Kurapati,
Wael Ali Ashmawi, and Jose Renau , Workshop on Architectural Research
Prototyping (WARP), held in conjunction with ISCA-33, June 2006.
2005 “μComplexity: Estimating Processor Design Effort”, Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau. 38th International Symposium on Microarchitecture (MICRO), November 2005.